SCAN and JTAG Insertion

麻薯

SCAN and JTAG Insertion

Week 1 Classes

Design Structures
Digital basics
verilog basics
ASIC flow
Chip Fabrication Process
ATE Overview
DFT Basics
Design Environment Setup
Linux commands



Week 2 Classes
Fault Models and Test Types
SCAN Design
SCAN Models
Types of Scan
Coverage Metrics
Scan Golden rules
Analysis of DFT DRC
DRC Fixing with examples


Week 3 Classes
Full scan insertion and stitching without compression
Generate test protocol files and understand
Synthesis Scan inserted netlist


Week 4 Classes
Basics/Need of Compression
Compression techniques
Scan insertion with compression
On-chip clocking for at-speed testing


Week 5 Classes
Hierarchical Scan Design
Top-Down Scan Insertion
Boundary scan basics
Boundary scan cell operation in detail
JTAG basics, operation, and state machine