Spacer engineered FinFET architectures

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In the past decade, high permittivity (k) spacer materials have emerged as the key enabler in enhancing device performance that provide a strong field coupling between the gate and the undoped underlap region; hence, reduces the increased source/drain resistance. However, it has limited applicability in high-performance circuits. The limitations are imposed due to an exorbitant increase in the fringe capacitance, that in turn, worsens the dynamic circuit performance. The other two inherent chal- lenges associated with FinFETs that limit their applicability in high- performance circuit applications, are the higher magnitude of parasitic resistances/capacitances (due to its three-dimensional [3D] nature) and fin width quantization. Therefore, digital circuit designers need to modify their designs taking into account these critical issues so as to improve the overall performance in terms of device/circuit parameters such as ION, IOFF, noise-immunity, and switching speed. At the device level, several researchers have focused on the integration of high-k materials as a gate dielectric and/or spacers. The fringing field phenomenon through high-k gate dielectric has been studied by few researchers from the circuit per- spectives. However, a comprehensive study of the impact of 3D fringing field, due to high-k spacers, on the device and circuit performances is still required. To the best of our knowledge, none of the research work has ever explored the direct impact of a fringing field in enhancing the dynamic circuit performance of high-k spacer devices.
This book primarily focuses on the novel device architecture that intelligently uses the high-permittivity spacer targeting high-performance device-circuit codesign (from the device level to the SRAM perspective) and its immunity to random statistical variations.

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