ESD Circuits and Devices

安哥拉

Contents
About the Author xvii
Preface xix
Acknowledgments xxv
Chapter 1 Electrostatic Discharge 1
1.1 Electricity and Electrostatics Discharge 1
1.1.1 Electricity and Electrostatics 1
1.1.2 Electrostatic Discharge 2
1.1.3 Key ESD Patents, Inventions, and Innovations 4
1.1.4 Table of ESD Defect Mechanisms 8
1.2 Fundamental Concepts of ESD Design 13
1.2.1 Concepts of ESD Design 13
1.2.2 Device Response to External Events 14
1.2.3 Alternate Current Loops 14
1.2.4 Switches 15
1.2.5 Decoupling of Current Paths 15
1.2.6 Decoupling of Feedback Loops 16
1.2.7 Decoupling of Power Rails 16
1.2.8 Local and Global Distribution 16
1.2.9 Usage of Parasitic Elements 16
1.2.10 Buffering 17
1.2.11 Ballasting 17
1.2.12 Unused Sections of a Semiconductor Device,
Circuit or Chip Function 18
1.2.13 Impedance Matching Between Floating and Non-Floating Networks 18
1.2.14 Unconnected Structures 18
1.2.15 Utilization of Dummy Structures and Dummy Circuits 18
1.2.16 Non-Scalable Source Events 18
1.2.17 Area Efficiency 18
1.3 Time Constants 19
1.3.1 Characteristic Times 19
1.3.2 Electrostatic and Magnetostatic Time Constants 19
1.3.2.1 Charge Relaxation Time 19
1.3.2.2 Magnetic Diffusion Time 19
1.3.2.3 Electromagnetic Wave Transit Time 20
1.3.3 Thermal Time Constants 21
1.3.3.1 Heat Capacity 22
1.3.3.2 Thermal Diffusion 22
1.3.3.3 Heat Transport Equation 22
1.3.4 Thermal Physics Time Constants 23
1.3.4.1 Adiabatic, Thermal Diffusion Time Scale
and Steady State 23
1.3.5 Semiconductor Device Time Constants 24
1.3.5.1 Depletion Region Transit Time 24
1.3.5.2 Silicon Diode Storage Delay Time 25
1.3.5.3 Bipolar Base Transit Time 25
1.3.5.4 Bipolar Turn-on Transient Time 26
1.3.5.5 Bipolar Turn-off Transient Time 26
1.3.5.6 Bipolar Emitter Transition Capacitance Charging Time 26
1.3.5.7 Bipolar Collector Capacitance Charging Time 26
1.3.5.8 Silicon Controlled Rectifier (SCR) Time Response 27
1.3.5.9 MOSFET Transit Time 27
1.3.5.10 MOSFET Drain Charging Time 27
1.3.5.11 MOSFET Gate Charging Time 28
1.3.5.12 MOSFET Parasitic Bipolar Response Time 28
1.3.6 Circuit Time Constants 28
1.3.6.1 Pad Capacitance 28
1.3.6.2 Half-pass Transmission Gates (TG) 29
1.3.6.3 n-Channel Half-pass Transistor Charging Time
Constant 29
1.3.6.4 Half-pass Transistor Transmission Gate
Discharge Time Constant 29
1.3.6.5 p-Channel Half-pass Transistor Charging
Time Constant 29
1.3.6.6 Inverter Propagation Delay Time Constants 30
1.3.6.7 High-to-low and Low-to-high Transition Time 30
1.3.6.8 Inverter Propagation Delay Time 30
1.3.6.9 Series n-channel MOSFETs Discharge Delay Time 31
1.3.6.10 Series p-channel MOSFETs Charge Delay Time 31
1.3.7 Chip Level Time Constants 32
1.3.7.1 Peripheral I/O Power Bus Time Constant 32
1.3.7.2 Core Chip Time Constant 33
1.3.7.3 Substrate Time Constants 33
1.3.7.4 Package Time Constants 34
1.3.8 ESD Time Constants 34
1.3.8.1 ESD Time Constants 34
1.3.8.2 ESD Events 34
1.3.8.3 Human Body Model Characteristic Time 35
1.3.8.4 Machine Model Characteristic Time 36
1.3.8.5 Charged Device Model Characteristic Time 36
viii CONTENTS
1.3.8.6 Charged Cable Model Characteristic Time 37
1.3.8.7 Cable Discharge Event (CDE) Model 37
1.3.8.8 Charged Cassette Model Characteristic Time 38
1.3.8.9 Transmission Line Pulse (TLP) Model
Characteristic Time 38
1.3.8.10 Very Fast Transmission Line Lulse (VF-TLP)
Model Characteristic Time 39
1.4 Capacitance, Resistance and Inductance and ESD 39
1.4.1 The Role of Capacitance 39
1.4.2 The Role of Resistance 40
1.4.3 The Role of Inductance 41
1.5 Rules of Thumb and ESD 42
1.5.1 ESD Design an ‘‘ESD Ohm’s Law’’: A Simple
ESD Rule-of-Thumb Design Approach 42
1.6 Lumped versus Distributed Analysis and ESD 43
1.6.1 Current and Voltage Distributions 43
1.6.2 Lumped versus Distributed Systems 43
1.6.3 Distributed Systems: Ladder Network Analysis 45
1.6.4 Resistor–Inductor–Capacitor (RLC) Distributed Systems 46
1.6.5 Resistor–Capacitor (RC) Distributed Systems 52
1.6.6 Resistor–Conductance (RG) Distributed Systems 55
1.7 ESD Metrics and Figures of Merit 57
1.7.1 Chip level ESD Metrics 57
1.7.1.1 Chip Mean Pin Power-To-Failure 57
1.7.1.2 Chip Pin Standard Deviation Power-To-Failure 58
1.7.1.3 Chip Mean Pin Power-To-Failure to ESD
Specification Margin 58
1.7.1.4 Worst Case Pin Power-To-Failure to Specification
ESD Margin 58
1.7.1.5 Total ESD Area to Total Chip Area Ratio 59
1.7.1.6 ESD Area to I/O Area Ratio 59
1.7.2 Circuit Level ESD Metrics 59
1.7.2.1 Circuit ESD Protection Level to ESD Loading
Effect 60
1.7.2.2 Circuit Performance to ESD Loading Effect 60
1.7.2.3 ESD Area to Total Circuit Area Ratio 60
1.7.2.4 Circuit ESD Level to Specification Margin 60
1.7.3 Device ESD Metric 61
1.7.3.1 ESD Area Percentage Utilization Factor 61
1.7.3.2 ESD Robustness to ESD Loading Effect Ratio 61
1.7.3.3 Power-to-Failure to Maximum Power
Condition 61
1.7.4 ESD Quality and Reliability Business Metrics 62
1.8 Twelve Steps to Building an ESD Strategy 63
1.9 Summary and Closing Comments 64
Problems 65
References 66
CONTENTS ix
Chapter 2 Design Synthesis 71
2.1 Synthesis and Architecture of a Semiconductor Chip for ESD Protection 71
2.2 Electrical and Spatial Connectivity 72
2.2.1 Electrical Connectivity 72
2.2.2 Thermal Connectivity 73
2.2.3 Spatial Connectivity 73
2.3 ESD, Latchup, and Noise 73
2.3.1 Noise 74
2.3.2 Latchup 75
2.4 Interface Circuits and ESD Elements 75
2.5 ESD Power Clamps Networks 78
2.5.1 Placement of ESD Power Clamps 80
2.6 ESD Rail-to-Rail Devices 82
2.6.1 Placement of ESD Rail-to-Rail Networks 84
2.6.2 Peripheral and Array I/O 84
2.7 Guard Rings 87
2.8 Pads, Floating Pads, and No Connect Pads 88
2.9 Structures Under Bond Pads 88
2.10 Summary and Closing Comments 90
Problems 90
References 91
Chapter 3 Electrostatic Discharge (ESD) Design: MOSFET Design 95
3.1 Basic ESD Design Concepts 95
3.1.1 Channel Length and Linewidth Control 102
3.1.2 ACLV Control 103
3.1.3 MOSFET ESD Design Practices 107
3.2 ESD MOSFET Design: Channel Width 109
3.2.1 n-Channel MOSFET Design: Channel Width 109
3.3 ESD MOSFET Design: Contact 109
3.3.1 Gate-To-Contact Spacing 110
3.3.2 Contact-To-Contact Space 114
3.3.3 End Contacts 118
3.3.4 Contacts to Isolation Edge 118
3.4 ESD MOSFET Design: Metal Distribution 119
3.4.1 MOSFET Metal Bus Design and Current Distribution 119
3.4.2 MOSFET Ladder Network Model 119
3.4.3 MOSFET Wiring: Anti-Parallel Current Distribution 123
3.4.4 MOSFET Wiring: Parallel Current Distribution 126
3.5 ESD MOSFET Design: Silicide Masking 129
3.5.1 Silicide Mask Design 129
3.5.2 Silicide Mask Design Over Source and Drain 130
3.5.3 Silicide Mask Design Over Gate 131
3.5.4 Silicide and Segmentation 132
3.6 ESD MOSFET Design: Series Cascode Configurations 133
3.6.1 Series Cascode MOSFET 133
3.6.2 Integrated Cascode MOSFETs 134
x CONTENTS
3.7 ESD MOSFET Design: Multi-Finger Design Integration of
Coupling and Ballasting Techniques 137
3.7.1 Grounded-Gate Resistor-Ballasted MOSFET 137
3.7.2 Soft Substrate Grounded-Gate Resistor-Ballasted MOSFET 139
3.7.3 Gate-Coupled Domino Resistor-Ballasted MOSFET 140
3.7.4 MOSFET Source-Initiated Gate-Bootstrapped Resistor-
Ballasted multi-Finger MOSFET With MOSFET 142
3.7.5 MOSFET Source-Initiated Gate-Bootstrapped Resistor
Ballasted Multi-Finger MOSFET With Diode 143
3.8 ESD MOSFET Design: Enclosed Drain Design Practice 144
3.9 ESD MOSFET Interconnect Ballasting Design 145
3.10 ESD MOSFET Design: Source and Drain Segmentation 147
3.11 Summary and Closing Comments 148
Problems 149
References 150
Chapter 4 Electrostatic Discharge (ESD) Design: Diode Design 153
4.1 ESD Diode Design: ESD Basic 153
4.1.1 Basic ESD Design Concepts 153
4.1.2 ESD Diode Design: ESD Diode Operation 155
4.2 ESD Diode Design: Anode 156
4.2.1 p Diffusion Anode Width Effect 156
4.2.2 p Anode Contacts 158
4.2.3 p Anode Silicide to Edge Design 158
4.2.4 p Anode to n Cathode Isolation Spacing 160
4.2.5 p Anode Diode End Effects 160
4.2.6 Circular and Octagonal ESD Diode Design 162
4.3 ESD Diode Design: Interconnect Wiring 162
4.3.1 Parallel Wiring Design 163
4.3.2 Anti-Parallel Wiring Design 164
4.3.3 Quantized Tapered Parallel and Anti-Parallel Wiring 164
4.3.4 Continuous Tapered Anti-Parallel and Parallel Wiring 164
4.3.5 Perpendicular (or Broadside) Wiring with Center-Fed Design 165
4.3.6 Perpendicular (or Broadside) with Uniform Metal Width 166
4.3.7 Perpendicular (or Broadside) Wiring with T-Shaped Extensions 167
4.3.8 Metal Design for Structures Under Bond Pads 168
4.4 ESD Diode Design: Polysilicon-Bound Diode Designs 168
4.4.1 ESD Design Issues with Polysilicon-Bound Diode Structures 170
4.5 ESD Diode Design: n-Well Diode Design 171
4.5.1 n-Well Diode Wiring Design 171
4.5.2 n-Well Contact Density 172
4.5.3 n-Well ESD Design, Guard Rings, and Adjacent Structures 173
4.6 ESD Diode Design: n/p Substrate Diode Design 175
4.7 ESD Diode Design: Diode String 175
4.7.1 ESD Design: Diode String Current–Voltage Relationship 178
4.7.2 ESD Design: Diode String Design—Architecture and the Design 183
4.7.3 Diode String Elements in Multiple I/O Environments 183
CONTENTS xi
4.7.4 Integration of Signal Pads 184
4.7.5 ESD Design: Diode String Design—Darlington Amplification 186
4.7.6 ESD Design: Diode String Design—Area Scaling 192
4.8 ESD Diode Design: Triple-Well Diodes 193
4.9 ESD Design: BiCMOS ESD Design 198
4.9.1 p/n-Well Diode ESD Structure with High Resistance
Implanted Sub-Collector 199
4.9.2 STI-Bound p/n-Well Diode with Deep Trench
(DT) Isolation Structure 200
4.9.3 STI-Bound p/n-Well Diode with Trench Isolation
(TI) Structure 201
4.10 Summary and Closing Comments 203
Problems 203
References 204
Chapter 5 Silicon on Insulator (SOI) ESD Design 209
5.1 SOI ESD Basic Concepts 209
5.2 SOI ESD Design: MOSFET with Body Contact (T-Shaped layout) 213
5.3 SOI ESD Design: SOI Lateral Diode Structure 216
5.3.1 SOI Lateral Diode Design 217
5.3.2 SOI Lateral Diode Perimeter Design 217
5.3.3 SOI Lateral Diode Channel Length Design 217
5.3.4 SOI Lateral p/n/n Diode Structure 219
5.3.5 SOI Lateral p/p/n Diode Structure 220
5.3.6 SOI Lateral p/p/n/n Diode Structure 220
5.3.7 Ungated SOI Lateral p/p/n/n Diode Structure 221
5.3.8 SOI Lateral Diode Structures and SOI MOSFET Halos 221
5.4 SOI ESD Design: Buried Resistors (BR) Elements 221
5.5 SOI ESD Design: SOI Dynamic Threshold MOSFET (DTMOS) 223
5.6 SOI ESD Design: Dual-Gate (DG) MOSFETs 225
5.7 SOI ESD Design: FinFET Structure 226
5.8 SOI ESD Design: Structures in the Bulk Substrate 228
5.9 SOI ESD Design: SOI-To-Bulk Contact Structures 229
5.10 Summary and Closing Comments 229
Problems 230
References 231
Chapter 6 Off-Chip Drivers (OCD) and ESD 235
6.1 Off-Chip Drivers (OCD) 235
6.1.1 Off Chip Drivers I/O Standards and ESD 236
6.1.2 OCD: ESD Design Basics 237
6.1.3 OCD: CMOS Asymmetric Pull-Up/Pull-Down 237
6.1.4 OCD: CMOS Symmetric Pull-Up/Pull-Down 239
6.1.5 OCD: Gunning Transceiver Logic (GTL) 241
6.1.6 OCD: High Speed Transceiver Logic (HSTL) 242
6.1.7 OCD: Stub Series Transceiver Logic (SSTL) 243
6.2 Off-Chip Drivers: Mixed-Voltage Interface 244
xii CONTENTS
6.3 Off-Chip Drivers Self-Bias Well OCD Networks 244
6.3.1 OCD: Self-Bias Well OCD Networks 246
6.3.2 ESD Protection Networks for Self-Bias Well OCD Networks 246
6.4 Off-Chip Drivers: Programmable Impedance (PIMP) OCD Networks 249
6.4.1 OCD: Programmable Impedance (PIMP) OCD Networks 251
6.4.2 ESD Input Protection Networks for PIMP OCDs 251
6.5 Off-Chip Drivers: Universal OCDs 252
6.6 Off-Chip Drivers: Gate-Array OCD Design 253
6.6.1 Gate-Array OCD ESD Design Practices 253
6.6.2 Gate-Array OCD Design: Usage of Unused Elements 253
6.6.3 Gate-Array OCD Design: Impedance Matching of
Unused Elements 255
6.6.4 OCD ESD Design: Power Rails Over Multi-Finger MOSFETs 255
6.7 Off-Chip Drivers: Gate Modulated Networks 256
6.7.1 OCD Gate-Modulated MOSFET ESD Network 256
6.7.2 OCD Simplified Gate-Modulated Network 257
6.8 Off-Chip Driver ESD Design: Integration of Coupling and
Ballasting Techniques 258
6.8.1 Ballasting and Coupling 258
6.8.2 MOSFET Source-Initiated Gate-Bootstrapped Resistor-
Ballasted Multi-Finger MOSFET with Diode 258
6.8.3 MOSFET Source-Initiated Gate-Bootstrapped Resistor-
Ballasted Multi-Finger MOSFET with MOSFET 260
6.8.4 Gate-Coupled Domino Resistor-Ballasted MOSFET 261
6.9 Off-Chip Driver ESD Design: Substrate-Modulated Resistor-
Ballasted MOSFET 262
6.10 Summary and Closing Comments 264
Problems 265
References 267
Chapter 7 Receiver Circuits and ESD 271
7.1 Receivers and ESD 271
7.1.1 Receivers and Receiver Delay Time 271
7.1.2 Receiver Performance and ESD Loading Effect 272
7.2 Receivers and ESD 273
7.2.1 Receivers and HBM 273
7.2.2 Receivers and CDM 274
7.3 Receivers and Receiver Evolution 275
7.3.1 Receiver Circuits with Half-Pass Transmission Gate 276
7.3.2 Receivers with Full-Pass Transmission Gate 279
7.3.3 Receivers, Half-Pass Transmission Gate, and Keeper Network 281
7.3.4 Receivers, Half-Pass Transmission Gate, and the
Modified Keeper Network 284
7.4 Receiver Circuits with Pseudo-Zero VT Half-Pass
Transmission Gates 286
7.5 Receiver Circuits with Zero Transmission Gate 289
7.6 Receiver Circuits with Bleed Transistors 291
CONTENTS xiii
7.7 Receiver Circuits with Test Functions 292
7.8 Receiver With Schmitt Trigger Feedback Networks 293
7.9 Bipolar Transistor Receivers 296
7.9.1 Bipolar Single Ended Receiver Circuits 296
7.9.2 Bipolar Differential Receiver Circuits 298
7.10 Summary and Closing Comments 299
Problems 300
References 301
Chapter 8 SOI ESD Circuits and Design Integration 303
8.1 SOI ESD Design Integration 303
8.1.1 SOI Versus Bulk CMOS ESD Design Advantages 304
8.1.2 SOI Versus Bulk CMOS ESD Design Layout Disadvantages 305
8.1.3 SOI Design Layout: T-Shaped Layout Style 305
8.1.4 SOI Design Layout: Mixed-Voltage Interface (MVI)
T-Shaped Layout Style 308
8.2 SOI ESD Design: Diode Design 311
8.3 SOI ESD Diode Design: Mixed Voltage Interface (MVI)
Environments 316
8.4 SOI ESD Networks in SOI cpu with Aluminum (Al) Interconnects 318
8.5 SOI ESD Design in Copper (Cu) Interconnects 321
8.6 SOI ESD Design with Gate Circuitry 322
8.7 SOI and Dynamic Threshold ESD Networks 324
8.8 SOI Technology and Miscellaneous ESD Issues 325
8.9 Summary and Closing Comments 326
Problems 326
References 327
Chapter 9 ESD Power Clamps 331
9.1 ESD Power Clamp Design Practices 331
9.2 ESD Power Clamps: Diode-Based 333
9.2.1 ESD Power Clamps: Series Diode Strings as Core Clamp 333
9.2.2 ESD Power Clamps: Series Diode Strings as Core
Clamps—Cladded Design Concept 336
9.2.3 ESD Power Clamps: Series Diode Strings as Core
Clamps—Boosted Design Concept 338
9.2.4 ESD Power Clamps: Series Diode Strings as Core
Clamps—Cantilever Design Concept 338
9.2.5 ESD Power Clamps: Triple-Well Series Diodes
as Core Clamps 340
9.2.6 ESD Power Clamps: SOI Series Diodes ESD Power Clamps 343
9.3 ESD Power Clamps: MOSFET-Based 344
9.3.1 CMOS RC-Triggered MOSFET ESD Power Clamp 344
9.3.2 Mixed-Voltage Interface RC-Triggered ESD Power Clamp 347
9.3.3 Voltage-Triggered MOSFET ESD Power Clamps 350
9.3.4 Modified RC-Triggered MOSFET ESD Power Clamps 351
9.3.5 RC-Triggered MOSFET ESD Power Clamp Placement 352
xiv CONTENTS
9.4 ESD Power Clamps: Bipolar-Based 352
9.4.1 Bipolar ESD Power Clamp: Voltage-Triggered
ESD Power Clamps 352
9.4.2 Bipolar ESD Power Clamp: Zener Breakdown
Voltage-Triggered 353
9.4.3 Bipolar ESD Power Clamp: BVCEO Voltage-Triggered
ESD Power Clamps 354
9.4.4 Bipolar ESD Power Clamp: Mixed-Voltage Interface
Forward-Bias Voltage and BVCEO-Breakdown
Synthesized Bipolar ESD Power Clamps 360
9.4.5 Bipolar ESD Power Clamp: Ultra Low-Voltage
Forward-Biased Voltage-Trigger 365
9.4.6 Bipolar ESD Power Clamp: Capacitively-Triggered 369
9.5 ESD Power Clamps: Silicon Controlled Rectifier-Based 371
9.5.1 Silicon Controlled Rectifier (SCR) ESD Power Clamps 371
9.6 Summary and Closing Comments 373
Problems 374
References 376
Index 379